中斷 Interrupt

原理：
CPU在正常執行工作時，由CPU內部或外部產生例外的request，要求 CPU suspend working job，做些必要的處理，以滿足各種預料外的狀況。

種類：
有兩種 硬體中斷 and 軟體中斷
硬體中斷：
硬體 能夠利用CPU的 interrupt request signal 來通知CPU中斷
軟體中斷：
CPU自己發出

處理interrupt原則
1.當下 CPU狀態記錄下來
2.跳到中斷處理程式做中斷處理


S3C2440 user manual第十四章有提及 interrupt controller
1.提供60個 interrupt sources, including DMA controller, UART, IIC, USB host and device, RTC(INT_TICK:RTC Time tick interrupt)[INT_RTC:RTC alarm interrupt].
2.interrupt request分兩種 FIQ(fast interrupt request) and IRQ(normal interrupt request)
3.CPU會根據硬體優先權 把結果寫到 interrupt pending register (紀錄哪個中斷產生)
，S3C2440A有兩個 interrupt pending registers: source pending register (SRCPND) and interrupt pending register(INTPND) 負責紀錄哪個中斷需要產生
如果要中斷來源要產生中斷，相對應SRCPND = 1 and INTPND = 1
4. interrupt mask register 負責作遮罩 讓某個中斷disable


INTERRUPT PRIORITY GENERATRING BLOCK
有32個 interrupt requests
先由6個 arbiter(仲裁者)x
決定誰的中斷可以採納 轉成 req0~5
最後交給第7個中斷來決定

arbiter
每個仲裁者 有one bit arbiter mode control(ARB_MODE) and two bits of selection control signals(ARB_SEL)
ARB_MODE 則負責啟動or 關閉 the function - 調整優先權
ARB_SEL 調整 interrupt 優先權順序


INTERRUPT CONTROLLER SPECIAL REGISTERS
1. source pending register (SRCPND)：所有 interrupt request from the interrupt sources 被登記到 source pending register
SRCPND 位置在 0x4A000000 R/W
0 = The interrupt has not been requested
這樣來說 哪個interrupt source要產生interrupt 先在此註冊(registe)
ex. 啟動RTC tick interrupt
設定此register為(0x1<<8)

2. interrupt mode register: 紀錄 interrupt request mode: FIQ and IRQ
0 = IRQ mode
1 = FIQ mode
順帶一提
只有一個interrupt能夠被設定為FIQ mode in the interrupt controller
(our system doesn't use this much)

3. interrupt mask register(INTMSK): 負責作遮罩
0 = interrupt service is available
1= interrupt service is masked
[so HWIntItem has function Enable() and Disable()
void Enable(){INTMSK &= ~(0x1<<8)}
In RTC init will call CHWIntItem::Enable to unmask RTC tick]

4. priority register ::負責控制arbiter 跟上述 interrupt priority generating block and interrupt priority有關
[Register, Address, R/W, Description, Reset Value]
[PRIORITY,0x4A00000C, R/W, IRQ priority register, 0x7F]
擁有21bit
0~6 bit 分別控制 arbiter 0~6 是否要調整priority
0 = priority does not rotate
1 = priority rotate enable

7~20 bit 分別去調整priority優先順序
可參考14-5
7-8 bit 負責作arbiter 0 priority調整
00 = REQ 1-2-3-4
01 = REQ 2-3-4-1
10 = REQ 3-4-1-2
11 = REQ 4-1-2-3
arbiter0 有四個 interrupt request
REQ1/EINT0
REQ2/EINT1
REQ3/EINT2
REQ4/EINT3
default value is 00
[our system does not use this register for some purpose]

5. interrupt pending register(INTPND)
bit in the pending register shows whether the corresponding interrupt request has the highest priority.
Only one bit can be set to 1. in INTPNDD.
Manual 中有提到 in 14-144
"Like the SRCPND register, this register has to be cleared in the interrupt service routine after clearing the SRCPND register."
clearpending function can set 1 and 5


continue
INTERRUPT OFFSET (INTOFFSET)
(not used in system)
The value in the INTOFFSET show which interrupt request of IRQ mode is in the INTPND register.
This bit can be cleared automatically by clearing SRCPND and INTPND.

SUB SOURCE PENDING(SUBSRCPND) REGISTER
indicate the interrupt request status.
1 = the interrupt source has asserted the interrupt request

INTERRUPT SUBMASK(INTSUBMSK) REGISTER
Determine which interrupt source is masked. The masked interrupt source will not be serviced.
1 = interrupt service is masked.
The function is the same with INTMSK. the difference is interrupt source.
ex. INTMSK第九個bit 負責 INT_WDT_AC97
INTSUBMSK 第13個bit 負責INT_WDT
第14個bit 負責INT_AC97


Reference:
http://www.eforth.com.tw/Csoc/eSOCFM/esoc_dol/AN/AN0001.pdf
S3C2440 user manual